Analysis and design of a high power millimeter-wave power amplifier in a SiGe BiCMOS technology

Our current society is characterized by an ever increasing need for bandwidth leading towards the exploration of new parts of the electromagnetic spectrum for data transmission. This results in a rising interest and development of millimeter-wave (mm-wave) circuits which hold the promise of short range multi-gigabit wireless transmissions at 60GHz. These relatively new applications are to co-exist with more established mm-wave consumer products including satellite systems in the Ka-band (26.5GHz - 40GHz) allowing e.g.: video broadcasting, voice over IP (VoIP), internet acces to remote areas, ... Both need significant linear power amplification due to the high attenuation typical for this part of the spectrum, however, satellite systems demand a saturated output power which is easily an order of magnitude larger (output powers in excess of 30dBm / 1W). Monolithic microwave integrated circuits (MMICs) employing III-V chip technologies, e.g.: gallium arsenide (GaAs), gallium nitride (GaN), have historically been the preferred choice to implement efficient mm-wave power amplifiers (PA) with a high saturated output power (>30dBm). To further increase the commercial viability of consumer products in this market segment a low manufacturing cost for the power amplifier, together with the possible integration of additional functions, is highly desirable. These features are the strongpoint of silicon based chip technologies like CMOS and SiGe BiCMOS. However, these technologies have a breakdown voltage typically below 2V for nodes capable of millimeter-wave applications while III-V transistors with equivalent frequency performance demonstrate breakdown voltages in excess of 8V. Because of this, output powers of CMOS and SiGe BiCMOS Ka-band power amplifiers rarely exceed 20dBm which poses the main hurdle for using these technologies in satellite communication (SATCOM). To overcome the limited output power of a single amplifying cell in a silicon technology, caused by the low breakdown voltage, multiple power amplifiers cells need to have their output power effectively combined on-chip. This requires the on-chip integration of high-Q passives within a relative small area to realize both the impedance transformation, to create the optimal load impedance for the different amplifier cells, and implement an efficient on-chip power combination network. Compared to III-V technologies this is again a challenge due to the use of a silicon substrate which introduces higher losses. Once a large enough on-chip output power is created, the issue of launching this signal to the outside world remains. Moreover, due to the limited efficiency of mm-wave PAs, the generated on-chip heat will increase when larger output power are required. This means a chipto-board interface with a low thermal resistance and a low loss electrical connection needs to be devised. Proof of the viability of silicon as a serious candidate for the integration of medium and high power Ka-band amplifiers will only be delivered by long term research and the actual creation of such an amplifier. In this context, the initial goal for the presented work is proposed. This consists of the creation of a power amplifier with a saturated output power above 24dBm (preferably 27dBm), a gain larger than 20dB and an efficiency in excess of 10% (preferably 15%). These specifications where conceived with the precondition of using a 250nm SiGe BiCMOS technology (IHP’s SG25H3) with an fT of 110GHz and a collector to emitter breakdown voltage in open base conditions (BVCEO) of 2.3V. The use of this technology is a significant challenge due to the limited speed, rule of thumb is to have at least one fifth of the fT as the operating frequency, which reflects in the attainable power added efficiency (PAE). On the other hand, proving the possible implementation in this “older” technology shows great potential towards the future integration in a fast technology (e.g.: IHP’s SG13G2, ft =300GHz). Next to issues caused by limitations of the chip technology, the proposed specifications allows to identify generic difficulties with high power silicon PA design, e.g.: design of efficient on-chip power combiners, thermal management, single-ended to differential conversion, ... As this work is of an academic nature the intention of this design was to leave the beaten track and explore alternative topologies. This has led to the adoption of a driver stage using translinear loops for biasing and a transformer-type Wilkinson power combiner previously only used in cable television (CATV) applications. Although the power combiner showed 2dB more loss than expected due to higher than expected substrate losses, both topologies show promise for further integration. Furthermore, an in-depth analysis was performed on the output stage which uses positive feedback to increase its gain. The entire design consists of a four-way power combining class AB power amplifier together with test structures of which the performance was verified by means of probing. Due to the previously mentioned higher than expected loss in the on-chip power combiner, the total output power and power added efficiency (PAE) was 2dB lower than expected from simulations. The result is a saturated output power at 32GHz of 24.1dBm with a PAE of 7.2% and a small signal gain of 25dB. This demonstrates the capability of SiGe BiCMOS to implement PA’s for medium-power mm-wave applications. Moreover, to the best of the author’s knowledge, this PA achieves the second highest saturated output power when comparing SiGe BiCMOS PA’s with center frequency in or close to the Ka-band. The 1dB compression point of this amplifier lies at 22.7dBm which is close to saturated output power and results in a low spectral regrowth when compared to commercial GaAs PA’s (compared with 2MBaud 16QAM input signal at 10dB back-off). Many possible improvements to this design remain. The most important would be the re-design of the on-chip power combiner, possibly with a floating ground shield, to reduce the losses and increase the total output power and PAE. Also the porting of the design to a faster chip technology might result in a considerable increase of the output stage efficiency at the cost of needing to combine more amplifier cells. The transition to a faster chip technology would additionally allow to use this design for alternative mm-wave applications like automotive radar at 79GHz andWiGig at 60GHz

A digitally controlled threshold adjustment circuit in a 0.13um SiGe BiCMOS technology for receiving multilevel signals up to 80Gbps

In this paper, a high bandwidth digitally controlled threshold adjustment circuit is proposed which can be used for demodulating high-speed multi-level signals. Simulations of the bandwidth are presented together with measurements of the control currents to indicate the threshold adjustment capability. A bandwidth above 80GHz in a 0.13µm SiGe BiCMOS technology and a threshold tunable between ±160mV in steps of 0.6mV is achieved, allowing very precise control of the threshold level. This allows the circuit to accurately position the threshold on the eye-crossing of a high speed multi-level signals. By applying this circuit to demodulate a duobinary signal over a 40GHz channel, a data rate of up to 80Gbps can be achieved

A 16 channel high-voltage driver with 14 bit resolution for driving piezoelectric actuators

A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design DAC together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a built-in output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string DAC which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and resampling of the output voltages

Analysis and design of a high power, high gain SiGe BiCMOS output stage for Use in a millimeter-wave power amplifier

In this paper a high gain, high power output stage designed in a 250nm SiGe BiCMOS technology is presented. The used topology together with a discussion on the stability of the output stage is explained in detail. In order to increase the gain of the output stage and thus increases the attainable power added efficiency (PAE), positive feedback is used. Furthermore a formula predicting the input impedance of a common base transistor at high frequencies is deducted which explains and predicts the magnitude of the feedback mechanism. The output stage achieves a peak gain of 14.4dB at 31GHz with a maximum output power of 22dBm

Adaptive transmit-side equalization for serial electrical interconnects at 100 Gb/s using duobinary

The ever-increasing demand for more efficient data communication calls for new, advanced techniques for high speed serial communication. Although newly developed systems are setting records, off-line determination of the optimal equalizer settings is often needed. Well-known adaptive algorithms are mainly applied for receive-side equalization. However, transmit-side equalization is desirable for its reduced linearity requirements. In this paper, an adaptive sign-sign least mean square equalizer algorithm is developed applicable for an analog transmit-side feed-forward equalizer (FFE) capable of transforming non-return-to-zero modulation to duobinary (DB) modulation at the output of the channel. In addition to the derivation of the update strategy, extra algorithms are developed to cope with the difficult transmit-receive synchronization. Using an analog six tap bit-spaced equalizer, the algorithm is capable of optimizing DB communication of 100Gb/s over 1.5-m Twin-Ax cable. Both simulations and experimental results are presented to prove the capabilities of the algorithm demonstrating automated determination of FFE parameters, such that error-free communication is obtained (BER<10(-13) using PRBS9)

On-Chip transmitter and receiver front-ends for ultra-broadband wired and optical-fiber communications

Increasing line rates beyond 56Gb/s is a big challenge for transceiver front-ends. We discuss recent developments towards 100Gb/s copper, +56Gb/s multi-channel single-mode VCSEL links and segmented MZM drivers for advanced modulation

100 Gb/s serial transmission over copper using duo-binary signaling

At last year’s DesignCon we presented duo-binary signaling as an alternative for PAM4 for data rates of 56 Gb/s and higher over copper. This paper explores the feasibility of using duo-binary signaling for 100 Gb/s serial transmission over copper. It includes an in-depth comparison between duo-binary and other signaling schemes regarding the acceptable channel loss, the tolerable crosstalk and jitter and the power consumption for serial data rates up to 100 Gb/s, and we study what the channel requirements are to be able to use duo-binary signaling for 100 Gb/s serial transmission over copper

84 Gbit/s SiGe BiCMOS duobinary serial data link including Serialiser/Deserialiser (SERDES) and 5-tap FFE

The increasing demand for bandwidth fuels the development towards high data rate electrical serial links. These links generally suffer from considerable frequency-dependent loss, introducing the need for equalisation at 10 Gbit/s and higher. Modulation schemes with improved spectral efficiency, with respect to non-retrun to zero (NRZ), combined with feed-forward equalisation (FFE), allow increasing the chip-to-chip data rate with the drawback of a more complex, e.g. multi-level, receiver (Rx). The use of duobinary modulation (DB) is presented to realise a high-speed serial link. The increase in complexity of a DB Rx is limited, whereas the required channel bandwidth compared with NRZ is reduced. Furthermore, the need for equalisation when compared with PAM4 is reduced as the required roll-off that is needed to create a duobinary modulated signal from an NRZ stream can incorporate the frequency-dependent loss of the link